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STV3208 8 x 8 discrete cosine transform (dct) july 1992 pqfp44 (plastic package) . 0 to 27mhz pixel rate in single precision mode, . 0 to 20 mhz pixel rate in double precision mode . forward and inverse 8 x 8 trans- form . 9-bit two's complement pixel format . 12-bit two's complement coefficient format . optimized accuracy for 8-bit two's complement pixel format . selectable scanning of coefficient blocks . fully ttl and cmos compatible . cmos technology . single +5 volt power supply . maximum power dissipation : 750mw at 27mhz order codes part number temperature range package stv3200cp 0 to 70 o c dip 40 stv3200cv 0 to 70 o c pqfp44 3208-01.tbl dip40 (plastic package) description the STV3208 is a dedicated circuit for the 8 x 8 discrete cosine transform(dct) computation.two- dimensional forward dct (fdct) or inverse dct (idct) is performed for 8 x 8 block sizes and a pixel rate up to 27mhz. the circuit architecture is fully bidirectional with 9-bit magnitude pixel data bus and a 12-bit magnitude coefficient data bus pro- grammed as input or output depending on the selection of fdct or idct. fdct idct data format pixel bus input output 9-bit 2's complement coefficient bus output input 12-bit 2's complement for the forward transform, the input pixels are coded on 9-bit 2's complement and the output coefficients are coded on 12-bit 2's complement. for the inverse transform, the data format is iden- tical with the coefficients used as input and the pixels used as output. two operating modes are provided : single preci- sion mode at a pixel rate up to 27 mhz, and double precision mode at a pixel rate up to 20 mhz. 1/17 free datasheet http://www..net/
3208-01a.eps / 3208-01b.eps pin connections 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 cc sync v f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 f css v nc test en clk ss d v v ss nc nc d0 d1 d2 d3 d4 d5 d6 d7 d8 pr sync cc nc s/d f/i oe ss v dip40 44 43 42 41 40 39 38 37 36 35 34 12 13 14 15 16 17 18 19 20 21 22 1 2 3 4 5 6 7 8 9 10 11 23 24 25 26 27 28 29 30 31 32 33 reserved s/d f/i oe reserved clk en test reserved reserved v ss v cc v cc v ss reserved reserved reserved d1 d0 f0 f1 f2 f3 reserved dsync pr d8 d7 d6 d5 d4 d3 d2 v ss css fsync f11 f10 f9 f8 f7 f6 f5 f4 pqfp44 pin identification pin number symbol type function / description 4-12 d0 to d8 i/o pixel data bus 13 pr input pixel range selection 14 dsync i/o pixel block synchronization signal 17 s/d input single/double precision selection 18 f/i input fdct/idct selection 19 oe input output three-state control 21 clk input clock signal 22 en input clock enable signal 23 test input test mode selection 26 css input zig zag selection 27 fsync i/o coefficient block synchronization signal 28-39 f0 to f11 i/o coefficient data bus 1,20,25 vss power ground 15,40 vcc power power supply 2,3,24 nc not connected 3208-02.tbl STV3208 2/17 free datasheet http://www..net/
3208-02.eps functional block diagram functional description 1. equations fdct idct n columns pixel data block coeff. data block m columns n lines m lines 3208-03.eps figure 1 the STV3208performs8 x 8 two dimensional discrete cosine transform according to the following formula: equations for 9-bit pixel data (pr pin set to low) : forward transform equation : f( u , v ) = round ? ? ? ? ? 1 4 c ( u ) c ( v ) i = 0 7 j = 0 7 d ( i , j ) cos ( 2 ? i + 1 ) u p 16 cos ( 2 ? j + 1 ) v p 16 ? ? ? ? ? STV3208 3/17 free datasheet http://www..net/
inverse transform equation : d( i , j ) = round ? ? ? ? ? 1 4 u = 0 7 v = 0 7 c ( u ) c ( v ) f ( u, v ) cos ( 2 ? i + 1 ) u p 16 cos ( 2 ? j + 1 ) v p 16 ? ? ? ? ? where c(u) = 1 ` ` 2 if u = 0 = 1 otherwise equations for 8-bit pixel data (pr pin set to high) : forward transform equation : f( u , v ) = round ? ? ? ? ? 1 2 c ( u ) c ( v ) i = 0 7 j = 0 7 d ( i,j ) cos ( 2 ? i + 1 ) u p 16 cos ( 2 ? j + 1 ) v p 16 ? ? ? ? ? inverse transform equation : d( i , j ) = round ? ? ? ? ? 1 8 u = 0 7 v = 0 7 c ( u ) c ( v ) f ( u, v ) cos ( 2 ? i + 1 ) u p 16 cos ( 2 ? j + 1 ) v p 16 ? ? ? ? ? where c(u) = 1 ` ` 2 if u = 0 = 1 otherwise 2. data flow ordering the pixel block is scanned column by column (order 1) or line by line (order 2). if css is high, the coefficient block is scanned with a zig zag order. figure 2 shows the relation between pixels order and coefficient order. pixel order coefficient order order 1 1 9 17 25 33 41 49 57 ? 1 2 6 7 15162829 2 10 18 26 34 42 50 58 3 5 8 14 17 27 30 43 3 11192735435159 4 9 131826314244 4 12202836445260 1012192532414554 5 13212937455361 1120243340465355 6 14223038465462 2123343947525661 7 15233139475563 2235384851576062 8 16243240485664 3637495058596364 order 2 12345678 ? 1 3 4 10 11 21 22 36 9 10 11 12 13 14 15 16 2 5 9 12 20 23 35 37 17 18 19 20 21 22 23 24 6 8 13 19 24 34 38 49 25 26 27 28 29 30 31 32 7 14 18 25 33 39 48 50 33 34 35 36 37 38 39 40 15 17 26 32 40 47 51 58 41 42 43 44 45 46 47 48 16 27 31 41 46 52 57 59 49 50 51 52 53 54 55 56 28 30 42 45 53 56 60 63 57 58 59 60 61 62 63 64 29 43 44 54 55 61 62 64 3208-03.tbl figure 2a : data ordering (css high) STV3208 4/17 free datasheet http://www..net/
pixel order coefficient order order 1 1 9 17 25 33 41 49 57 ? 12345678 2 10 18 26 34 42 50 58 9 10 11 12 13 14 15 16 3 11192735435159 1718192021222324 4 12202836445260 2526272829303132 5 13212937455361 3334353637383940 6 14223038465462 4142434445464748 7 15233139475563 4950515253545556 8 16243240485664 5758596061626364 order 2 12345678 ? 1 9 17 25 33 41 49 57 9 10 11 12 13 14 15 16 2 10 18 26 34 42 50 58 17 18 19 20 21 22 23 24 3 11 19 27 35 43 51 59 25 26 27 28 29 30 31 32 4 12 20 28 36 44 52 60 33 34 35 36 37 38 39 40 5 13 21 29 37 45 53 61 41 42 43 44 45 46 47 48 6 14 22 30 38 46 54 62 49 50 51 52 53 54 55 56 7 15 23 31 39 47 55 63 57 58 59 60 61 62 63 64 8 16 24 32 40 48 56 64 3208-04.tbl figure 2b : data ordering (css low) if css is low, the coefficient block is scanned line by line and the pixel block is scanned column by column, or the coefficient block is scanned column by column and the pixel block is scanned line by line. 3. data format coefficients format is 12-bit 2's complement, cor- responding to the range -2048 to 2047. there are 2 possible ranges for pixel data : 9-bit two's complement magnitude (see figure 3) the pixel data range is -256 to +255. in this case the pr pin must be set to 0 for idct. d8 is the most significant bit and d0 the least significant bit for the pixel data. a clipping to the range -256 to +255 is performed before outputting reconstructed pixels after an idct. 8-bit two's complement magnitude (see figure 4) pixel data range is -128 to +127. in this case d0 must be set to 0 and the pr pin must be set to 1 for idct. d8 is the most significant bit and d1 the least significant bit for the pixel data. a clipping to the range -128 to +127 is performed before output- ting reconstructed pixels after an idct. this mode may be used for intra picture coding. in this case, pixel data range is 0 to 255. for a fdct, the most significant bit of input pixel data (d8) must be inverted before entering the chip. this isequiva- lent to substract 128 to the input pixel data. note that this operation will only have effect on the dc value f(0,0). for an idct, the most significant bit of output pixel data (d8) must be inverted. this is equivalent to add 128 to the output pixel data. 3208-04.eps figure 3 STV3208 5/17 free datasheet http://www..net/
4. block flow depending on the application, blocks may be en- tered in different way. latent period : the latent period between input data and corre- sponding output results is 167 clock cycles (if fdct is selected)or 163 clock cycles (if idct is selected) in single precision mode (s/d pin set to 1). this means that the first data of the resulting block is provided 137 clock cycles (if fdct is selected) or 135 clock cycles (if idct is selected) in double precision mode (s/d pin set to 0). latency forward dct inverse dct s/d = 1 single precision 167 cycles 163 cycles s/d = 0 double precision 137 cycles 135 cycles synchronization signals : an input block synchronization signal must be pro- vided. the input pin for this signal is dsync if fdct is selected and fsync if idct is se- lected.this signal is active low and must not be active more than one clock cycle and during the first clock cycle after power-up.this signal must be active with the first data of each input block or group of blocks. an output block synchronization signal is provided. the output pin for this signal is fsync if fdct is selected and dsync if idct is selected. this signal is active with the first data of each output block or group of blocks. the output synchronization signal is equal to the input synchronization signal delayed from the la- tent period (see figure 5). continuous block flow inputs data are fed continously with one new item data at each clock cycle and output data is provided continously with one new result data item at each clock cycle. the input synchronization signal can be provided for each input block. in this case the output syn- chronization pulse is provided for each output block (figure 6). an other way is to provide a synchroni- zation pulse only for the first block of a group of blocks. in this case, only one synchronizationpulse is provided for the first output block (figure 7). 3208-05.eps figure 4 3208-06.eps figure 5 STV3208 6/17 free datasheet http://www..net/
3208-07.eps figure 6 : continuous block flow 1 3208-08.eps figure 7 : continuous block flow 2 continuous block flow with bypass of irrevelant data it is possible to process a block flow including irrelevant data (corresponding to line suppression for example) as if it was a continous block flow. one way is to stop the clock signal during the irrelevant data occurence. another way is to use the clock enable signal (en) which allows to stop the chip internal clock during irrelevant data occurrence (see figure 8) STV3208 7/17 free datasheet http://www..net/
burst block flow (see figure 9) single blocks (or groups of block) may not be continous. in other words, delay cycles between two blocks (or groups of block) may exist. during these delay cycles, the clock is still running and the chip continues to perform computations. the con- straint is that the internal pipe line must not be broken when the new block occurs.to take this constraint into account, the number of delay cycles (nc) must respect one of the following conditions : 1 - the numberof delay cycles (nc) is greater than or equal to the latency. in this case the pipe line is empty (all the relevant data has been output) when a new input block processing starts. 2 - the number of delay cycles (nc) is a multiple of 64. in this case, the input data always re- mains synchronous with the internal pipe line. mixed fdct/idct (see figure 10) in some low frequency application, it could be cost effective to use only one chip to compute all the dct required by the coding scheme. blocks must be fed in a burst fashion with at least the latency time between the last pixel of input pixels for fdct and the first pixel of input coefficients for idct. the same delay must be respected between the last pixel of input coefficients for idct and the first pixel of input pixels for fdct. 3208-09.eps figure 8 : continuous block flow with irrelevant data 3208-10.eps figure 9 : burst block flow STV3208 8/17 free datasheet http://www..net/
64 cyc les block a 64 cycles block b 9 64 cycles fdct (a) 64 cycles fdct (b) 64 cycles block c 64 cycles block d 64 cycles idct (c) 64 cycles idct (d) 7 3208-11.eps figure 10 : mixed 8 x 8 fdct/idct example waveforms (double precision) precision selection for single precision mode, the s/d pin must be high. in this case, the maximum rating for pixel is 27 mhz. for double precision mode, the s/d pin must be low. in this case, the maximum rating for pixel is 20 mhz. 5. pins description clk : clock signal data pins d0 to d8 : 9-bit bidirectional pixel data bus pins. direction is programmed by the f/i pin : f/i state d0 to d8 direction high input low output data is loaded (when input) or settled (when out- put) on rising edge of clk. d0 is the least signifi- cant bit and d8 the most significant one. note that for the optimized mode for 8-bit 2's c pixel data, d1 is the least significant bit and d0 must be set to 0. msb lsb d8 d7 d6 d5 d4 d3 d2 d1 d0 pin -256 128 64 32 16 8 4 2 1 weight dsync : pixel data block synchronization signal. this pin is bidirectional with the direction pro- grammed by the f/i pin (like d0 to d8). dsync is active (low level during one clock cycle only) with the first pixel data of a block (or a group of blocks). f0 to f11 : 12-bit bidirectional coefficient data bus pins. direction is programmed by the f/i pin : f/i state f0 to f11 direction high output low input STV3208 9/17 free datasheet http://www..net/
data is loaded (when input) or settled (when output) on rising edge of clk. f0 is the least significant bit and f11 the most significant one. msb lsb f11 f10 f9 f8 f7 f6 f5 f4 f3 f2 f1 f0 pin -2048 1024 512 256 128 64 32 16 8421 weight fsync : coefficient data block synchronization signal. this pin is bidirectional with the direction programmed by the f/i pin (like f0 to f11). fsync is active (low level during one clock cycle only ) with the first coefficient data of a block (or a group of blocks). control pins f/i : forward or inverse selection. when f/i is high, forward dct is performed, when f/i is low, inverse dct is performed. s/d : single or double precision. when s/d is high, single precision is selected. when s/d is low, dou- ble precision is selected. css : coefficient scanning selection. when css is high, zig zag scanning of coefficient block is se- lected. when css is low, row scanning of coeffi- cient block is selected. pr : pixel range selection. if pr is low, pixel range is -256 to +255. if pr is high, pixel range is -128 to +127. oe : output enable. this signal is active low. when oe is high, all outputs (defined by the f/i pin state) are forced to the high impedance state. en : enable. this signal is active low. when en is high, internal states of the chip are frozen. when en becomes low, execution restarts. en must go to high state when clk is high. state function f/i is high f/i is low forward dct inverse dct s/d is high s/d is low single precision double precision css is high css is low zig zag scanning of coefficients row scanning of coefficients pr is high pr is low 8-bit 2's c pixel data 9-bit 2's c pixel data oe is high oe is low high impedance outputs outputs active en is high en is low internal clock is stopped internal clock runs power supply and ground pins v cc : +5 volt power supply v ss : ground potential others : test. this pin is reserved and must be low in normal mode. 3208-12.eps 6. accuracy characteristics the accuracy characteristics have been measured according to the following scheme : STV3208 10/17 free datasheet http://www..net/
a: characteristics of idct. error between the idct computed with 64-bit floating point accuracy and the idct computed by the STV3208 is measured. measures have been done according to the ccitt wgxv method single precision double precision peak error 1 1 peak mean square error 0.0403 0.0258 overall mean square error 0.0287 0.0200 peak mean error 0.0125 0.0041 overall mean error 0.0050 0.0000062 9-bit pixels 8-bit pixels single precision double precision single precision double precision exact value 97.1 % 98.0 % 99.96 % 99.97 % errors of 1 lsb 2.9 % 2.0 % 0.04 % 0.03 % errors of 2lsb 0% 0% 0% 0% b: characteristics of fdct. error between the fdct computed with 64-bit floating point accuracy and the fdct computed by the STV3208 is measured. 9-bit pixels 8-bit pixels single precision double precision single precision double precision exact value 93.6 % 96.9 % 93.6 % 96.9 % errors of 1 lsb 6.4 % 4.1 % 6.4 % 4.1 % errors of 2lsb 0% 0% 0% 0% c: characteristics of fdct followed by an idct. error between the source picture and the fdct computed by the STV3208 followed by an idct computed by the STV3208 is measured. 9-bit pixels 8-bit pixels single precision double precision single precision double precision exact value 89.3 % 90.6 % 99.88 % 99.92 % errors of 1 lsb 10.7 % 9.4 % 0.12 % 0.08 % errors of 2lsb 0% 0% 0% 0% STV3208 11/17 free datasheet http://www..net/
3208-13.eps note : fsync will be in unknown state after the power up during a count of cycles equal to the latency. timing waveforms synchonization signals timing diagram for a forward transform 3208-14.eps note : dsync will be in unknown state after the power up during a count of cycles equal to the latency. synchronization signals timing diagram for an inverse transform 3208-15.eps output enable signal timing waveforms 3208-16.eps control static signal timing waveforms STV3208 12/17 free datasheet http://www..net/
3208-17.eps note : en signal must change from low to high level during the high level of clk signal. timing waveforms (continued) enable signal timing waveforms 3208-18.eps clock timing waveforms 3208-19.eps output timing waveforms STV3208 13/17 free datasheet http://www..net/
symbol parameter test condition s min. typ. max. unit v cc operating voltage 4.75 5.25 v i cc supply current : f clk =27mhz f clk = 0 mhz c load = 50 pf on all outputs. all inputs at v cc or v ss 150 1 ma ma v il v ih input voltage level (except clk) logic low logic high v cc =5 0.25 v 2 0.8 v v v il(clk) v ih(clk) clock signal logic low logic high 2.5 0.5 v v high impedance input leakage : i/o buffers input buffers v in =v ss to v cc -5 -1 +5 +1 m a m a v ol v oh output voltage level : logic low i load = 500 m a logic high i load = -500 m a v cc = 4.75 v 2.7 0.4 v v c in input capacitance v offset = 2.5 v, f = 1 mhz 10 pf 3208-05.tbl electrical characteristics absolute maximum ratings supply voltage (v cc ) : 6 volts operating temperature range : 0 to 70 o c dc electrical characteristics operating conditions : v ss = 0 volt, t a = 0 to 70 o c, v cc =5 v 5% unless otherwise specified ac electrical characteristics operating conditions : v ss = 0 volt, t a = 0 to 70 o c, v cc =5v 5 % unless otherwise specified outputs loads : capacitance = 50 pf, current logic low = 500 m a test load on outputs : v ref v cc i ol i oh 50 m f output = 1.5v 3208-20.eps STV3208 14/17 free datasheet http://www..net/
symbol parameter min. typ. max. unit t r rising time from 0.5 to 3.5 v 10 ns t f falling time from 3.5 to 0.5 v 10 ns t ch clock high pulse width s/d = 1 s/d = 0 15 24 ns ns t cl clock low pulse width s/d = 1 s/d = 0 15 24 ns ns t clk clock cycle duration s/d = 1 s/d = 0 37 50 ns ns t sdcl data setup time from clk 8ns t hdcl data hold time from clk 0ns t do output data delay from clk 15 ns t en1 enable hold time from clk 0ns t en2 enable rising edge setup time from clk 5ns t en3 enable falling edge setup time from clk s/d = 1 s/d = 0 0 0 ns ns t off delay from oe to output going to high impedance state 15 ns t on delay from oe to output going to high or low state 15 ns t co f/i , css, pr, s/d setup time from beginning of input stream 100 ns 3208-06.tbl timings are measured between threshold voltage of 1.5 v unless otherwise specified. STV3208 15/17 free datasheet http://www..net/
40 i a1 l b2 e d e3 f b1 e 21 120 b pm-dip40.eps package mechanical data 40 pins - plastic dip dimensions millimeters inches min. typ. max. min. typ. max. a1 0.63 0.025 b 0.45 0.018 b1 0.23 0.31 0.009 0.012 b2 1.27 0.050 d 52.58 2.070 e 15.2 16.68 0.598 0.657 e 2.54 0.100 e3 48.26 1.900 f 14.1 0.555 i 4.445 0.175 l 3.3 0.130 dip40.tbl STV3208 16/17 free datasheet http://www..net/
e2 (seating plane) e1 e d2 d1 d b a2 a a1 k f l c e 22 23 12 33 11 1 34 44 pmpqfp44.eps package mechanical data 44 pins - plastic quad flat pack dimensions millimeters inches min. typ. max. min. typ. max. a 3.40 0.134 a1 0.25 0.01 a2 2.55 2.80 3.05 0.10 0.11 0.12 b 0.35 0.50 0.014 0.020 c 0.13 0.23 0.005 0.009 d 16.95 17.20 17.45 0.667 0.677 0.687 d1 13.90 14.00 14.10 0.547 0.551 0.555 d2 10.00 0.394 e 1.00 0.039 e 16.95 17.20 17.45 0.667 0.677 0.687 e1 13.90 14.00 14.10 0.547 0.551 0.555 e2 10.00 0.394 f 1.60 0.063 k0 o (min.), 7 o (max.) l 0.65 0.80 0.95 0.025 0.031 0.037 pqfp44.tbl information furnished is believed to be accurate and reliable. however, sgs-thomson microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no licence is granted by implication or otherwise under any patent or patent rights of sgs-thomson microelectronics. specifications mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. sgs-thomson microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of sgs-thomson microelectronics. ? 1994 sgs-thomson microelectronics - all rights reserved purchase of i 2 c components of sgs-thomson microelectronics, conveys a license under the philips i 2 c patent. rights to use these components in a i 2 c system, is granted provided that the system conforms to the i 2 c standard specifications as defined by philips. sgs-thomson microelectronics group of companies australia - brazil - china - france - germany - hong kong - italy - japan - korea - malaysia - malta - morocco the netherlands - singapore - spain - sweden - switzerland - taiwan - thailand - united kingdom - u.s.a. STV3208 17/17 free datasheet http://www..net/

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